@pistolero @Machismo @Nozakero @surk⁠⁠⁠⁠⁠⁠⁠⁠⁠⁠⁠⁠⁠⁠⁠�... So Zhang Fuxin was bullied into bolting on the entire X86 instruction set on a formerly MIPS3 compatible RISC chip that had its own SIMD additions. Then they forked QEMU to pass all the X86 opcodes directly through virtualization.

The result was the Loongson 3 series: dog shit CPUs that failed at being X86 and failed at the concept of RISC by having more instructions than every big instruction chip.

Retardation abounds in IT.