nostr:npub1ch8nj9yu4676fnwkzacu28mt4y002ezeryqyuhzfnzjw560sq5fqaysw60 nostr:npub1qh2njwwrsmdnlqdrn6ktu2k32txpumqzcln778t2mdasa85kep7shvugqs nostr:npub1dphugmh2e88uc7ntlfsjjxeqstv8qlz4c30zuqe0zwwwqx2xg7mqhut7jj nostr:npub1kwugrw5qdm7qzgw4zduc6g8mj3z0wztn54av9vmth9uks4zdugeqp6qdsv So Zhang Fuxin was bullied into bolting on the entire X86 instruction set on a formerly MIPS3 compatible RISC chip that had its own SIMD additions. Then they forked QEMU to pass all the X86 opcodes directly through virtualization.

The result was the Loongson 3 series: dog shit CPUs that failed at being X86 and failed at the concept of RISC by having more instructions than every big instruction chip.

Retardation abounds in IT.