So, there is this thing called the Serial Peripheral Interface. It's a very simple full-duplex serial protocol used for short-distance communications between chips on the same PCB. It is much faster than another popular PCB protocol, I²C. A single SPI link can usually do at least 20 Mbit/sec, and often more - so it's a reasonable choice for non-volatile memories, small display modules, programmable op-amps, ADCs, DACs, and whatnot. The advantage of SPI is that compared to a parallel bus, it takes up fewer I/O pins - three shared lanes (serial in, serial out, clock), plus a "chip select" signal for every peripheral on the bus. In contrast, a standard 8-bit parallel bus would require eight shared data lines + clock + "chip select". 

The trade-off is that the bit rate is proportionately lower because you're sending bits one by one - but again, 20 Mbps is often enough. Except... well, sometimes, it isn't. If you have a 320x240x24bpp display module and you're sending data at 20 Mbit/sec, you're looking at a screen refresh rate of 10 fps. If you have a 1 MB serial DRAM chip, it would take about 400 ms to read or write the whole thing.

So, at some point, chip manufacturers came up with "dual SPI". This didn't actually use any extra I/O pins - it simply turned serial in / serial out into a pair of bidirectional, half-duplex lines. That doubled the bit rate in many applications, pretty much for free.

Still, that wasn't quite enough, so the next innovation was "quad SPI". Quad SPI added two more data lines, for a total of 5 + num_of_peripherals. This offered a 4x bit rate of the base protocol and made many people happy.

But hold on, we're getting to the next logical milestone: some STM chips offer "octo SPI" and "hexadeca SPI", with 8 and 16 data lines. And I guess my only question is... did they just invent a parallel bus with extra steps?