Is it possible to multiply a clock in a Verilog testbench? It absolutely does not need to be synthesizable, this is purely for simulation
I can generate clocks of different frequencies with "always begin" + delays but I want to guarantee a edge alignment or a phase shift

Boosts for visibility appreciated!
#verilog #fpga #hardware #openhardware 

 Is there interest in a game audio programming tutorial?
Writing my sound system took ages and a lot of the things I ended up doing (dynamic occlusion, head-related transfer function, effects with custom frequency responses) aren't well documented for game devs anywhere
#gamedev #indiedev